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max1069 58.6ksps, 14-bit, 2-wire serial adc in a 14-pin tssop ________________________________________________________________ maxim integrated products 1 19-2652; rev 0; 10/02 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. general description the max1069 is a low-power, 14-bit successive- approximation analog-to-digital converter (adc). the device features automatic power-down, an on-chip 4mhz clock, a +4.096v internal reference, and an i 2 c-compatible 2-wire serial interface capable of both fast and high-speed modes. the max1069 operates from a single supply and con- sumes 5mw at the maximum conversion rate of 58.6ksps. autoshutdown powers down the device between conversions, reducing supply current to less than 50? at a 1ksps throughput rate. the option of a separate digital supply voltage allows direct interfacing with +2.7v to +5.5v digital logic. the max1069 performs a unipolar conversion on its single analog input using its internal 4mhz clock. the full-scale analog input range is determined by the inter- nal reference or by an externally applied reference volt- age ranging from 1v to av dd . the four address select inputs (add0?dd3) allow up to sixteen max1069 devices on the same bus. the max1069 is packaged in a 14-pin tssop and offers both commercial and extended temperature ranges. refer to the max1169 for a 16-bit device in a pin-compatible package. applications hand-held portable applications medical instruments battery-powered test equipment solar-powered remote systems receive signal strength indicators system supervision features high-speed i 2 c-compatible serial interface 400khz fast mode 1.7mhz high-speed mode +4.75v to +5.25v single supply +2.7v to +5.5v adjustable logic level internal +4.096v reference external reference: 1v to av dd internal 4mhz conversion clock 58.6ksps sampling rate autoshutdown between conversions low power 5.0mw at 58.6ksps 4.2mw at 50ksps 2.0mw at 10ksps 0.23mw at 1ksps 3? in shutdown small 14-pin tssop package ordering information part temp range pin- package inl ( lsb ) MAX1069ACUD 0 c to +70 c 14 tssop 1 max1069bcud 0 c to +70 c 14 tssop 2 max1069ccud 0 c to +70 c 14 tssop 3 max1069aeud* -40 c to +85 c 14 tssop 1 max1069beud* -40 c to +85 c 14 tssop 2 max1069ceud* -40 c to +85 c 14 tssop 3 14 13 12 11 10 9 8 1 2 3 4 5 6 7 add3 ref refadj agnds add2 sda scl dgnd top view max1069 ain agnd av dd dv dd add0 add1 tssop pin configuration i 2 c is a trademark of philips corp. autoshutdown is a trademark of maxim integrated products, inc. * future product?ontact factory for availability.
max1069 58.6ksps, 14-bit, 2-wire serial adc in a 14-pin tssop 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av dd to agnd .........................................................-0.3v to +6v dv dd to dgnd .........................................................-0.3v to +6v agnd to dgnd.....................................................-0.3v to +0.3v agnds to agnd...................................................-0.3v to +0.3v ain, ref, refadj to agnd....................-0.3v to (av dd + 0.3v) scl, sda, add_ to dgnd.......................................-0.3v to +6v maximum current into any pin............................................50ma continuous power dissipation (t a = +70 c) 14-pin tssop (derate 9.1mw/ c above +70 c) .........727mw operating temperature ranges: max1069_cud ..................................................0 c to +70 c max1069_eud ................................................-40 c to +85 c storage temperature range .............................-65 c to +150 c junction temperature ......................................................+150 c lead temperature (soldering, 10s) .................................+300 c electrical characteristics (av dd = +4.75v to +5.25v, dv dd = +2.7v to +5.5v, f scl = 1.7mhz (33% duty cycle), f sample = 58.6ksps, v ref = +4.096v, external ref- erence applied to ref, refadj = av dd , c ref = 10f, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) parameter symbol conditions min typ max units dc accuracy (note 1) resolution 14 bits max1069a 1 max1069b 2 relative accuracy (note 2) inl max1069c 3 lsb max1069a, no missing codes 1 max1069b, no missing codes 1 differential nonlinearity dnl max1069c, no missing codes 1 lsb offset error 25mv offset-error temperature coefficient 1.0 ppm/ c gain error (note 3) 0.25 0.5 %fsr gain temperature coefficient 0.1 ppm/ c dynamic performance (f in(sine wave) = 1khz, v in = v ref(p-p) , f sample = 58.6ksps) signal-to-noise plus distortion sinad 81 84 db total harmonic distortion thd up to the 5th harmonic -99 -86 db spurious-free dynamic range sfdr 87 102 db signal-to-noise ratio snr 82 84 db full-power bandwidth fpbw -3db point 4 mhz full-linear bandwidth sinad > 81db 20 khz conversion rate (figure 11) fast mode 7.1 7.5 conversion time (scl stretched low) t conv high-speed mode 5.8 6 s fast mode 19 throughput rate (note 4) f sample high-speed mode 58.6 ksps internal clock frequency f clk 4 mhz track/hold acquisition time t acq (note 5) 1100 ns
max1069 58.6ksps, 14-bit, 2-wire serial adc in a 14-pin tssop _______________________________________________________________________________________ 3 electrical characteristics (continued) (av dd = +4.75v to +5.25v, dv dd = +2.7v to +5.5v, f scl = 1.7mhz (33% duty cycle), f sample = 58.6ksps, v ref = +4.096v, external ref- erence applied to ref, refadj = av dd , c ref = 10f, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) parameter symbol conditions min typ max units fast mode 50 aperture delay (figure 11c) (note 6) t ad high-speed mode 30 ns fast mode 100 aperture jitter (figure 11c) t aj high-speed mode 100 ps analog input (ain) input voltage range v ain 0v ref v input leakage current on/off-leakage current, v ain = 0v or av dd , no clock, f scl = 0 0.01 10 a input capacitance c in 35 pf internal reference (bypass refadj with 0.1? to agnd and ref with 10? to agnd) ref output voltage v ref 4.056 4.096 4.136 v t a = 0 c to +70 c 20 reference temperature coefficient tc ref t a = -40 c to +85 c 35 ppm/ c reference short-circuit current i refsc 10 4.136 ma refadj output voltage 4.056 4.096 4.000 v refadj input range for small adjustments, from 4.096v 60 mv external reference (refadj = av dd ) refadj buffer disable voltage pull refadj high to disable the internal bandgap reference and reference buffer av dd - 0.1 v refadj buffer enable voltage av dd - 0.4 v reference input voltage range (note 7) 1.0 av dd v v ref = +4.096v, v in = v ref(p-p) f in(sine wave) = 1khz, f sample = 62.1ksps 27 ref input current i ref v ref = +4.096v, shutdown 0.1 a digital inputs/outputs (scl, sda) input high voltage v ih 0.7 dv dd v input low voltage v il 0.3 dv dd v input hysteresis v hyst 0.1 dv dd v input current i in 10 a input capacitance c in 15 pf output low voltage v ol i sink = 3ma 0.4 v address select inputs (add3, add2, add1, add0) input high voltage 0.7 dv dd v input low voltage 0.3 dv dd v input hysteresis 0.1 dv dd v input current 10 a input capacitance 15 pf
max1069 58.6ksps, 14-bit, 2-wire serial adc in a 14-pin tssop 4 _______________________________________________________________________________________ electrical characteristics (continued) (av dd = +4.75v to +5.25v, dv dd = +2.7v to +5.5v, f scl = 1.7mhz (33% duty cycle), f sample = 58.6ksps, v ref = +4.096v, external ref- erence applied to ref, refadj = av dd , c ref = 10f, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) parameter sym b o l conditions min typ max units power requirements (av dd , agnd, dv dd , dgnd) analog supply voltage av dd 4.75 5.25 v digital supply voltage dv dd 2.7 5.5 v f sample = 58.6ksps 1.8 2.5 f sample = 10ksps 0.7 ma f sample = 1ksps 40 inter nal r efer ence ( p ow er ed d ow n b etw een conver si ons, r/ w = 0) shutdown 0.4 5.0 a f sample = 58.6ksps 1.8 2.5 f sample = 10ksps 1.4 ma f sample = 1ksps 1.1 ma internal reference (always on, r/ w = 1) shutdown 0.4 5 a f sample = 58.6ksps 0.90 1.8 f sample = 10ksps 0.36 ma f sample = 1ksps 40 analog supply current i avdd external reference (refadj = av dd ) shutdown 0.4 5 a f sample = 58.6ksps 260 400 f sample = 10ksps 65 f sample = 1ksps 6 digital supply current i dvdd shutdown 0.2 5 a power-supply rejection ratio psrr av dd = 5v 5%, full-scale input (note 8) 2 6 lsb/v timing characteristics for 2-wire fast mode (figure 1a and figure 2) serial clock frequency f scl 400 khz bus free time between a stop and a start condition t buf 1.3 s hold time for start condition t hd , sta 0.6 s low period of the scl clock t low 1.3 s high period of the scl clock t high 0.6 s setup time for a repeated start condition (sr) t su,sta 0.6 s data hold time t hd , dat (note 9) 0 900 ns data setup time t su , dat 100 ns rise time of both sda and scl signals, receiving t r (note 10) 20 + 0.1c b 300 ns fall time of sda transmitting t f (note 10) 20 + 0.1c b 300 ns setup time for stop condition t su , sto 0.6 s c ap aci ti ve load for e ach bus li ne c b 400 pf pulse width of spike suppressed t sp 50 ns
max1069 58.6ksps, 14-bit, 2-wire serial adc in a 14-pin tssop _______________________________________________________________________________________ 5 note 1: dc accuracy is tested at av dd = +5.0v and dv dd = +3.0v. performance at power-supply tolerance limits is guaranteed by power-supply rejection test. note 2: relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and offset have been calibrated. note 3: offset nullified. note 4: one sample is achieved every 18 clocks in continuous conversion mode. note 5: the track/hold acquisition time is two scl cycles as illustrated in figure 11. note 6: a filter on sda and scl delays the sampling instant and suppresses noise spikes less than 10ns in high-speed mode and 50ns in fast mode. note 7: adc performance is limited by the converter s noise floor, typically 480v p-p . note 8: psrr v (5.25v)- v (4.75v) 2 v 5.25v - 4.75v fs fs n ref = [] where n is the number of bits ( ). 14 t2 1 f acq scl = ? ? ? ? ? ? f 1 clocks f t sample scl c -1 =+ ? ? ? ? ? ? 8 onv electrical characteristics (continued) (av dd = +4.75v to +5.25v, dv dd = +2.7v to +5.5v, f scl = 1.7mhz (33% duty cycle), f sample = 58.6ksps, v ref = +4.096v, external ref- erence applied to ref, refadj = av dd , c ref = 10f, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) parameter sym b o l conditions min typ max units timing characteristics for 2-wire high-speed mode (figure 1b and figure 2) serial clock frequency f sclh (note 11) 1.7 mhz hold time, (repeated) start condition t hd , sta 160 ns low period of the scl clock t low 320 ns high period of the scl clock t high 120 ns setup time for a repeated start condition t su,sta 160 ns data hold time t hd , dat (note 9) 0 150 ns data setup time t su , dat 10 ns rise time of scl signal (current source enabled) t rcl (note 10) 10 80 ns rise time of scl signal after acknowledge bit t rcl1 (note 10) 20 160 ns fall time of scl signal t fcl (note 10) 20 80 ns rise time of sda signal t rda (note 10) 20 160 ns fall time of sda signal t fda (note 10) 20 160 ns setup time for stop condition t su , sto 160 ns c ap aci ti ve load for e ach bus li ne c b 400 pf pulse width of spike suppressed t sp 10 ns
max1069 58.6ksps, 14-bit, 2-wire serial adc in a 14-pin tssop 6 _______________________________________________________________________________________ note 9: a master device must provide a data hold time for sda (referred to v il of scl) in order to bridge the undefined region of scl s falling edge (see figure 1). note 10: c b = total capacitance of one bus line in pf. t r and t f measured between 0.3 ? dv dd and 0.7 ? dv dd . note 11: f scl must meet the minimum clock low time plus the rise/fall times. electrical characteristics (continued) (av dd = +4.75v to +5.25v, dv dd = +2.7v to +5.5v, f scl = 1.7mhz (33% duty cycle), f sample = 58.6ksps, v ref = +4.096v, external ref- erence applied to ref, refadj = av dd , c ref = 10f, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) figure 1. i 2 c serial interface timing t hd,sta t hd,sta t high t high t r t rcl t f t fcl t hd,sta s sr a scl sda t su,sta t su,sto t su,sto t rcl1 t r t f t buf t buf t low t su,dat t hd,dat t hd,dat ps t su,dat t hd,sta s sr a scl sda t su,sta t low p s hs-mode f/s-mode a. f/s-mode i 2 c serial interface timing b. hs-mode i 2 c serial interface timing t rda t fda parameters are measured from 30% to 70%. figure 2. load circuit v out v dd i ol = 3ma i oh = 0ma 400pf digital i/o
max1069 58.6ksps, 14-bit, 2-wire serial adc in a 14-pin tssop _______________________________________________________________________________________ 7 analog supply current vs. analog supply voltage (internal reference) max1069 toc01 av dd (v) i avdd (ma) 5.15 5.05 4.95 4.85 1.65 1.67 1.69 1.71 1.73 1.75 1.63 4.75 5.25 dv dd = 3v t a = +85 c t a = +70 c t a = +25 c t a = 0 c t a = -40 c 770 780 790 800 810 820 830 760 analog supply current vs. analog supply voltage (external reference) max1069 toc02 av dd (v) i avdd ( a) 5.15 5.05 4.95 4.85 4.75 5.25 dv dd = 3v t a = +85 c t a = +70 c t a = +25 c t a = 0 c t a = -40 c analog shutdown current vs. analog supply voltage max1069 toc03 av dd (v) i avdd (na) 5.15 5.05 4.95 4.85 200 100 300 400 500 600 700 0 4.75 5.25 t a = +85 c t a = +70 c t a = +25 c t a = 0 c t a = -40 c dv dd = 3v f sample = 0 r/w = 0 digital supply current vs. digital supply voltage max1069 toc04 dv dd (v) i dvdd ( a) 5.1 4.7 3.9 4.3 3.5 3.1 120 140 160 180 200 220 240 260 280 100 2.7 5.5 av dd = 5v t a = +85 c t a = -40 c digital shutdown current vs. digital supply voltage max1069 toc05 dv dd (v) i dvdd (na) 4.3 4.7 5.1 3.9 3.5 3.1 100 50 150 200 250 300 350 0 2.7 5.5 av dd = 5v f sample = 0 r/w = 0 t a = +70 c t a = +85 c t a = +25 c t a = 0 c t a = -40 c offset error vs. temperature max1069 toc06 temperature ( c) offset error ( v) 60 35 -15 10 -600 -400 -200 0 200 400 600 800 -800 -40 85 gain error vs. temperature max1069 toc07 temperature ( c) gain error (%fsr) 60 35 -15 10 -0.006 -0.004 -0.002 0 0.002 0.004 0.006 0.008 -0.008 -40 85 typical operating characteristics (dv dd = +3.0v, av dd = +5.0v, f scl = 1.7mhz (33% duty cycle), f sample = 58.6ksps, v ref = +4.096v, external reference applied to ref, refadj = av dd , c ref = 10f, t a = +25 c, unless otherwise noted.)
max1069 58.6ksps, 14-bit, 2-wire serial adc in a 14-pin tssop 8 _______________________________________________________________________________________ typical operating characteristics (continued) (dv dd = +3.0v, av dd = +5.0v, f scl = 1.7mhz (33% duty cycle), f sample = 58.6ksps, v ref = +4.096v, external reference applied to ref, refadj = av dd , c ref = 10f, t a = +25 c, unless otherwise noted.) supply current vs. conversion rate (high-speed mode, internal reference) max1069 toc08 conversion rate (ksps) supply current ( a) 60 50 30 40 20 10 200 400 600 800 1000 1200 1400 1600 1800 2000 0 070 internal reference, f scl = 1.7mhz i avdd , r/w = 1 i avdd , r/w = 0 i dvdd , r/w = 1 or 0 100 200 300 400 500 600 700 800 900 0 supply current vs. conversion rate (high-speed mode, external reference) max1069 toc09 conversion rate (ksps) supply current ( a) 60 50 30 40 20 10 070 external reference, f scl = 1.7mhz i dvdd , r/w = 1 or 0 i avdd , r/w = 1 or 0 supply current vs. conversion rate (fast mode, internal reference) max1069 toc10 conversion rate (ksps) supply current ( a) 20 15 10 5 200 400 600 800 1000 1200 1400 1600 1800 0 025 internal reference, f scl = 400khz i avdd , r/w = 1 i avdd , r/w = 0 i dvdd , r/w = 1 or 0 100 200 300 400 500 600 0 supply current vs. conversion rate (fast mode, external reference) max1069 toc11 conversion rate (ksps) supply current ( a) 20 15 10 5 025 external reference, f scl = 400khz i dvdd , r/w = 1 or 0 i avdd , r/w = 1 or 0
max1069 58.6ksps, 14-bit, 2-wire serial adc in a 14-pin tssop _______________________________________________________________________________________ 9 internal +4.096v reference voltage vs. analog supply voltage max1069 toc12 av dd (v) v ref (v) 5.15 5.05 4.95 4.85 4.080 4.085 4.090 4.095 4.100 4.075 4.75 5.25 dv dd = 3v t a = +85 c t a = +70 c t a = +25 c t a = 0 c t a = -40 c internal reference voltage vs. ref load max1069 toc13 i ref (ma) v ref (v) 5 4 3 2 1 3.95 4.00 4.05 4.10 4.20 3.90 06 f scl = 0 internal reference mode load applied to ref 4.15 5 10 15 20 25 30 35 0 external reference current vs. external reference voltage max1069 toc14 v ref (v) i ref ( a) 5 4 3 2 1 06 ain = agnds 58.6ksps f scl = 1.7mhz 19ksps f scl = 400khz external reference current and reference voltage vs. v refadj max1069 toc15 v refadj (v) i refadj ( a) v ref (v) 4.20 4.15 4.10 4.05 4.00 -20 -10 0 10 20 30 -30 4.00 4.05 4.10 4.15 4.20 4.25 3.95 3.95 4.25 ain = agnds i refadj v ref typical operating characteristics (continued) (dv dd = +3.0v, av dd = +5.0v, f scl = 1.7mhz (33% duty cycle), f sample = 58.6ksps, v ref = +4.096v, external reference applied to ref, refadj = av dd , c ref = 10f, t a = +25 c, unless otherwise noted.)
max1069 58.6ksps, 14-bit, 2-wire serial adc in a 14-pin tssop 10 ______________________________________________________________________________________ typical operating characteristics (continued) (dv dd = +3.0v, av dd = +5.0v, f scl = 1.7mhz (33% duty cycle), f sample = 58.6ksps, v ref = +4.096v, external reference applied to ref, refadj = av dd , c ref = 10f, t a = +25 c, unless otherwise noted.) signal-to-noise ratio vs. frequency max1069 toc16 frequency (khz) snr (db) 120 110 100 90 80 70 60 50 40 30 20 10 0 1 10 100 spurious-free dynamic range vs. frequency max1069 toc17 frequency (khz) sfdr (db) 120 110 100 90 80 70 60 50 40 30 20 10 0 1 10 100 differential nonlinearity vs. digital output code max1069 toc18 digital output code dnl (lsb) 12288 8192 4096 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 16384 total harmonic distortion vs. frequency max1069 toc19 frequency (khz) thd (db) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 1 10 100 sinad vs. frequency max1069 toc20 frequency (khz) sinad (db) 120 110 100 90 80 70 60 50 40 30 20 10 0 1 10 100 integral nonlinearity vs. digital output code max1069 toc21 digital output code inl (lsb) 12288 8192 4096 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 16384 fft max1069 toc22 frequency (khz) magnitude (db) 23.44 17.56 11.72 5.86 -120 -100 -80 -60 -40 -20 0 -140 0 29.30 f sample = 58.6ksps f in(sine wave) = 1khz v in = v ref(p-p)
detailed description the max1069 analog-to-digital converter (adc) uses successive-approximation conversion (sar) tech- niques and on-chip track-and-hold (t/h) circuitry to capture and convert an analog signal to a serial 14-bit digital output. the max1069 performs a unipolar conversion on its single analog input using its internal 4mhz clock. the full-scale analog input range is determined by the inter- nal reference or by an externally applied reference volt- age ranging from 1v to av dd . the flexible 2-wire serial interface provides easy con- nection to microcontrollers (cs) and supports data rates up to 1.7mhz. figure 3 shows the simplified func- tional diagram for the max1069 and figure 4 shows the typical application circuit. power supply to maintain a low-noise environment, the max1069 provides separate analog and digital power-supply inputs. the analog circuitry requires a +5v supply and consumes only 900a at sampling rates up to 58.6ksps. the digital supply voltage accepts voltages from +2.7v to +5.5v to ensure compatibility with low- voltage asics. the max1069 wakes up in shutdown mode when power is applied irrespective of the av dd and dv dd sequence. analog input and track/hold the max1069 analog input contains a track-and-hold (t/h) capacitor, t/h switches, comparator, and a switched capacitor digital-to-analog converter (dac) ( figure 5 ). as shown in figure 11c , the max1069 acquisition peri- od is the two clock cycles prior to the conversion peri- od. the t/h switches are normally in the hold position. during the acquisition period the t/h switches are in the track position and c t/h charges to the analog input signal. before a conversion begins, the t/h switches move to the hold position retaining the charge on c t/h as a sample of the analog input signal. during the conversion interval, the switched capacitive dac adjusts to restore the comparator input voltage to zero within the limits of 14-bit resolution. this is equiva- lent to transferring a charge of 35pf (v ain - v agnds ) from c t/h to the binary-weighted capacitive dac, max1069 58.6ksps, 14-bit, 2-wire serial adc in a 14-pin tssop ______________________________________________________________________________________ 11 pin description pin name function 1 dgnd digital ground 2 scl clock input 3 sda data input/output 4 add2 address select input 2 5 add1 address select input 1 6 add0 address select input 0 7dv dd digital power input. bypass to dgnd with a 0.1f capacitor. 8av dd analog power input. bypass to agnd with a 0.1f capacitor. 9 agnd analog ground 10 ain analog input 11 agnds analog signal ground. negative reference for analog input. connect to agnd. 12 refadj internal reference output and reference buffer input. bypass to agnd with a 0.1f capacitor. connect refadj to av dd to disable the internal bandgap reference and reference-buffer amplifier. 13 ref reference buffer output and external reference input. bypass to agnd with a 10f capacitor when using the internal reference. 14 add3 address select input 3
max1069 forming a digital representation of the analog input sig- nal. during the conversion period, the max1069 holds scl low (clock stretching). the time required for the t/h to acquire an input signal is a function of the analog input source impedance. if the input signal source impedance is high, lengthen the acquisition time by reducing f scl . the max1069 pro- vides two scl cycles (t acq ), in which the track-and- hold capacitance must acquire a charge representing the input signal. minimize the input source impedance (r source ) to allow the track-and-hold capacitance to charge within the allotted time. r source should be less than 12.9k ? for f scl = 400khz and less than 2.4k ? 58.6ksps, 14-bit, 2-wire serial adc in a 14-pin tssop 12 ______________________________________________________________________________________ figure 3. max1069 simplified functional diagram ain agnds control logic 4mhz internal oscillator output shift register t/h sar adc ref clock in out +4.096v reference refadj ref 5k ? add0 add1 add2 add3 dv dd av dd dgnd scl sda agnd 8 13 12 11 9 1 2 3 4 5 6 7 10 14 max1069 a v = 1.0 figure 4. typical application circuit ain ref 10 f 0.1 f refadj agnds av dd 0.1 f agnd dgnd analog source add1 add0 add2 scl sda dv dd 0.1 f 3.0v 5.0v c v dd sda scl r p r p add3 v ss 8 13 12 11 14 91 2 3 4 5 6 7 10 i 2 c address is 0110111 max1069
for f scl = 1.7mhz. r source is calculated with the fol- lowing equation: where r source is the analog input source impedance, f scl is the maximum system scl frequency, n is 14 (the number of bits of resolution), c in is 35pf (the sum of c t/h and input stray capacitance), and r in is 800 ? (the t/h switch resistances). to improve the input-signal bandwidth under ac conditions, drive ain with a wideband buffer (>4mhz) that can drive the adc? input capacitance and settle quickly (see the input buffer section). an rc filter at ain reduces the input track-and-hold switching transient by providing charge for c t/h . analog input bandwidth the max1069 features input-tracking circuitry with a 4mhz small-signal bandwidth. the 4mhz input band- width makes it possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the adc s sampling rate by using under- sampling techniques. use anti-alias filtering to avoid high-frequency signals being aliased into the frequency band of interest. analog input range and protection internal esd (electrostatic discharge) protection diodes clamp ain, ref, and refadj to av dd and agnds/agnd ( figure 6 ). these diodes allow the ana- log inputs to swing from (agnd - 0.3v) to (av dd + 0.3v) without causing damage to the device. for accu- rate conversions, the inputs must not go more than 50mv beyond their rails. if the analog inputs exceed 300mv beyond their rails, limit the current to 2ma. internal clock the max1069 contains an internal 4mhz oscillator that drives the sar conversion clock. during conversion, scl is held low (clock stretching). an internal register stores data when the conversion is in progress. when the max1069 releases scl, the master reads the conversion results at any clock rate up to 1.7mhz ( figure 11 ). digital interface the max1069 features an i 2 c-compatible, 2-wire serial interface consisting of a bidirectional serial data line (sda) and a serial clock line (scl). sda and scl facili- tate bidirectional communication between the max1069 and the master at rates up to 1.7mhz. the master (typically a microcontroller) initiates data trans- fer on the bus and generates scl. sda and scl require pullup resistors (500 ? or greater, figure 4 ). optional resistors (24 ? ) in series with sda and scl protect the device inputs from high-voltage spikes on the bus lines. series resistors also minimize crosstalk and undershoot of the bus signals. bit transfer one data bit is transferred during each scl clock cycle. nine clock cycles are required to transfer the data into or out of the max1069. the data on sda must remain stable during the high period of the scl clock pulse as changes in sda while scl is high are control signals (see the start and stop conditions section). both sda and scl idle high. start and stop conditions the master initiates a transmission with a start condi- tion (s), a high-to-low transition on sda with scl high. the master terminates a transmission with a stop con- dition (p), a low-to-high transition on sda while scl is high ( figure 7 ). the stop condition frees the bus and places all devices in f/s mode (see the bus timing section). use a repeated start condition (sr) in place r fin ( 22 ) c r source scl n in in ? 2 max1069 58.6ksps, 14-bit, 2-wire serial adc in a 14-pin tssop ______________________________________________________________________________________ 13 figure 5. equivalent input circuit c t/h ain agnds capacitive dac ref track hold track hold hold track *r source analog signal source *minimize r source to allow the track-and-hold capacitance (c t/h ) to charge to the analog signal source voltage within the allotted time (t acq ). max1069 figure 6. internal protection diodes ain refadj av dd agnd ref agnds max1069
max1069 of a stop condition to leave the bus active and in its current timing mode (see the hs-mode section). acknowledge bits successful data transfers are acknowledged with an acknowledge bit (a) or a not-acknowledge bit ( a ). both the master and the max1069 (slave) generate acknowl- edge bits. to generate an acknowledge, the receiving device must pull sda low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low during the high period of the clock pulse ( figure 8 ). to generate a not acknowledge, the receiver allows sda to be pulled high before the rising edge of the acknowledge-related clock pulse and leaves it high during the high period of the clock pulse. monitoring the acknowledge bits allows for detection of unsuccessful data transfers. an unsuccessful data transfer happens if a receiving device is busy or if a system fault has occurred. in the event of an unsuc- cessful data transfer, the master should reattempt com- munication at a later time. slave address a master initiates communication with a slave device by issuing a start condition followed by a slave address byte. as shown in figure 9, the slave address byte con- sists of 7 address bits and a read/write bit (r/ w ). when idle, the max1069 continuously waits for a start con- dition followed by its slave address. when the max1069 recognizes its slave address, it acquires the analog input signal and prepares for conversion. the first three bits (msbs) of the slave address have been factory programmed and are always 011 . connecting add3 add0 to dv dd or dgnd, programs the last four bits (lsbs) of the slave address high or low. since the max1069 does not require setup or configu- ration, the least significant bit (lsb) of the address byte (r/ w ) controls power-down. in external reference mode (refadj = av dd ), r/ w is a don t care. in internal refer- ence mode, setting r/ w = 1 places the device in nor- mal operation and setting r/ w = 0 powers down the internal reference following the conversion (see the internal reference shutdown section). after receiving the address, the max1069 (slave) issues an acknowledge by pulling sda low for one clock cycle. bus timing at power-up, the max1069 bus timing defaults to fast mode (f/s-mode), allowing conversion rates up to 19ksps. the max1069 must operate in high-speed mode (hs-mode) to achieve conversion rates up to 58.6ksps. figure 1 shows the bus timing for the max1069 2-wire interface. hs-mode at power-up, the max1069 bus timing is set for f/s- mode. the master selects hs-mode by addressing all devices on the bus with the hs-mode master code 0000 1xxx (x = don t care). after successfully receiving the hs-mode master code, the max1069 issues a not acknowledge allowing sda to be pulled high for one 58.6ksps, 14-bit, 2-wire serial adc in a 14-pin tssop 14 ______________________________________________________________________________________ figure 8. acknowledge bits 12 8 9 acknowledge not acknowledge scl s sda figure 7. start and stop conditions sp sr scl sda
clock cycle ( figure 10 ). after the not acknowledge, the max1069 is in hs-mode. the master must then send a repeated start followed by a slave address to initiate hs-mode communication. if the master generates a stop condition, the max1069 returns to f/s-mode. data byte (read cycle) initiate a read cycle to begin a conversion. a read cycle begins with the master issuing a start condition followed by seven address bits and a read bit (r/ w ). the standard i 2 c-compatible interface requires that r/ w = 1 to read from a device, however, since the max1069 does not require setup or configuration, the read mode is inherent and r/ w controls power-down (see the internal reference shutdown section). if the address byte is successfully received, the max1069 (slave) issues an acknowledge and begins conversion. as seen in figure 11 , the max1069 holds scl low dur- ing conversion. when the conversion is complete, scl is released and the master can clock data out of the device. the most significant byte of the conversion is available first and contains d13 to d6. the least signifi- cant byte contains d5 to d0 plus two trailing sub bits s1 and s0. data can be continuously converted as long as the master acknowledges the conversion results. issuing a not acknowledge frees the bus allowing the master to generate a stop or repeated start. applications information power-on reset when power is first applied, internal power-on reset cir- cuitry activates the max1069 in shutdown. when the internal reference is used, allow 12ms for the reference to settle when c ref = 10f and c refadj = 0.1f. automatic shutdown the max1069 automatic shutdown reduces the supply current to less than 0.6a between conversions. the max1069 i 2 c-compatible interface is always active. when the max1069 receives a valid slave address the device powers up. the device is then powered down again when the conversion is complete. the automatic shutdown function does not change with internal or external reference. when the internal reference is cho- sen, the internal reference remains active between con- versions unless internal reference shutdown is requested (see the internal reference shutdown section). internal reference shutdown the r/ w bit of the slave address controls the max1069 internal reference shutdown. in external reference mode (refadj = av dd ), r/ w is a don t care. in internal reference mode, setting r/ w = 1 places the device in normal operation and setting r/ w = 0 prepares the internal reference for shutdown. max1069 58.6ksps, 14-bit, 2-wire serial adc in a 14-pin tssop ______________________________________________________________________________________ 15 figure 10. f/s-mode to hs-mode transfer 123 0 0 0 89 4567 01xxx sr s f/s-mode hs-mode sda a figure 9. max1069 slave address byte scl sda 123 1 1 0 89 4567 add3 add2 add1 add0 r/w a acknowledge s
max1069 if the internal reference is used and r/ w = 0, shutdown occurs when the master issues a not-acknowledge bit while reading the conversion results. the internal refer- ence and internal reference buffer are disabled during shutdown, reducing the analog supply current to less than 1a. a dummy conversion is required to power up the inter- nal reference. the max1069 internal reference begins powering up from shutdown on the 9th falling edge of a valid address byte. allow 12ms for the internal refer- ence to settle before obtaining valid conversion results. reference voltage the max1069 provides an internal or accepts an exter- nal reference voltage. the adc input range is from v agnds to v ref (see the transfer function section). 58.6ksps, 14-bit, 2-wire serial adc in a 14-pin tssop 16 ______________________________________________________________________________________ figure 11. read cycle s 1 slave address 71 r number of bits p or sr 1 1 8 result #1 a 18 result #1 a 1 8 result a 18 result a 1 clock stretch t conv t acq a 8 result #2 a 1 clock stretch t conv t acq number of bits 89 567 bit3 bit2 bit1 bit0 a clock stretch t ad t acq t aj scl sda 123 d10 d12 d11 t conv 8 result #2 a 1 number of bits p or sr 1 a 1 8 result #n a 18 result #n clock stretch t conv t acq (most significant byte) (least significant byte) (most significant byte) (least significant byte) (least significant byte) (most significant byte) (most significant byte) (least significant byte) analog input track and hold track hold hold b. continuous conversions a. single conversion slave to master master to slave c. acquisition detail d13 4 r s 1 slave address a 711 clock stretch t acq t conv
internal reference the max1069 contains an internal 4.096v bandgap ref- erence. this bandgap reference is connected to refadj through a 5k ? resistor. bypass refadj with a 0.1f capacitor to agnd. the max1069 reference buffer has a unity gain to provide +4.096v at ref. bypass ref with a 10f capacitor to agnd when the internal reference is used ( figure 12 ). the internal reference is adjustable to 1.5% using the figure 13 circuit. external reference for external reference operation, disable the internal reference by connecting refadj to av dd . during con- version, an external reference at ref must deliver up to 100a of dc load current and have an output imped- ance of less than 10 ? . for optimal performance, buffer the reference through an op amp and bypass ref with a 10f capacitor. consider the max1069 s equivalent input noise (80v rms ) when choosing a reference. transfer function the max1069 has a standard unipolar transfer function with a valid analog input voltage range from v agnds to v ref . output data coding is binary with 1lsb = (v ref /2 n ) where n is the number of bits (14). code transitions occur halfway between successive-integer lsb values. figure 14 shows the max1069 input/output (i/o) transfer function. input buffer most applications require an input buffer amplifier to achieve 14-bit accuracy. if the input signal is multi- plexed, the input channel should be switched immedi- ately after acquisition, rather than near the end of or max1069 58.6ksps, 14-bit, 2-wire serial adc in a 14-pin tssop ______________________________________________________________________________________ 17 figure 12. internal reference 4.096v bandgap reference 5k ? sar adc ref 0.1 f 10 f ref refadj 4.096v agnd dgnd a v = 1.0 12 13 9 1 max1069 figure 13. adjusting the internal reference 4.096v bandgap reference 5k ? sar adc ref 0.1 f 10 f ref refadj 4.096v agnd dgnd a v = 1.0 12 13 9 1 max1069 0.1 f 150k ? 100k ? potentiometer 68k ? av dd 5.0v 8
max1069 after a conversion. this allows more time for the input buffer amplifier to respond to a large step-change in input signal. the input amplifier must have a high enough slew rate to complete the required output volt- age change before the beginning of the acquisition time. at the beginning of acquisition, the internal sam- pling capacitor array connects to ain (the amplifier out- put), causing some output disturbance. ensure that the sampled voltage has settled to within the required limits before the end of the acquisition time. if the frequency of interest is low, ain can be bypassed with a large enough capacitor to charge the internal sampling capacitor with very little ripple. however, for ac use, ain must be driven by a wide- band buffer (at least 4mhz), which must be stable with the adc s capacitive load (in parallel with any ain bypass capacitor used) and also settle quickly. refer to maxim s website at www.maxim-ic.com for application notes on how to choose the optimum buffer amplifier for your adc application. layout, grounding, and bypassing careful printed circuit (pc) layout is essential for the best system performance. boards should have sepa- rate analog and digital ground planes and ensure that digital and analog signals are separated from each other. do not run analog and digital (especially clock) lines parallel to one another, or digital lines underneath the device package. figure 4 shows the recommended system ground con- nections. establish an analog ground point at agnd and a digital ground point at dgnd. connect all analog grounds to the star analog ground. connect the digital grounds to the star digital ground. connect the digital ground plane to the analog ground plane at one point. for lowest-noise operation, make the ground return to the star ground s power-supply low impedance and make it as short as possible. high-frequency noise in the av dd power supply degrades the adc s high-speed comparator perfor- mance. bypass av dd to agnd with a 0.1f ceramic surface-mount capacitor. make bypass capacitor con- nections as short as possible. if the power supply is very noisy, connect a 10 ? resistor in series with av dd and a 4.7f capacitor from av dd to agnd to create a lowpass rc filter. definitions integral nonlinearity integral nonlinearity (inl) is the deviation of the values on an actual transfer function from a straight line. this straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function once offset and gain errors have been nullified. the max1069 inl is measured using the endpoint method. differential nonlinearity differential nonlinearity (dnl) is the difference between an actual step width and the ideal value of 1lsb. a dnl error specification of less than 1lsb guarantees no missing codes and a monotonic transfer function. aperture jitter aperture jitter (t aj ) is the sample-to-sample variation in the time between the samples ( figure 11 ). aperture delay aperture delay (t ad ) is the time from the falling edge of scl to the instant when an actual sample is taken ( figure 11 ). signal-to-noise ratio for a waveform perfectly reconstructed from digital sam- ples, signal-to-noise ratio (snr) is the ratio of full-scale analog input (rms value) to the rms quantization error (residual error). the ideal, theoretical minimum analog- to-digital noise is caused by quantization error only and results directly from the adc s resolution (n bits): snr = ((6.02 ? n) + 1.76)db in reality, noise sources besides quantization noise exist, including thermal noise, reference noise, clock jit- ter, etc. therefore, snr is computed by taking the ratio of the rms signal to the rms noise, which includes all spectral components minus the fundamental, the first five harmonics, and the dc offset. 58.6ksps, 14-bit, 2-wire serial adc in a 14-pin tssop 18 ______________________________________________________________________________________ figure 14. unipolar transfer function agnds input voltage (lsb) binary output code (lsb) 012 3 16384 1lsb = v ref 16383 16381 0...000 0...001 0...010 0...011 1...111 1...110 1...101 1...100 v ref v ref
signal-to-noise plus distortion signal-to-noise plus distortion (sinad) is the ratio of the fundamental input frequency s rms amplitude to rms equivalent of all other adc output signals. effective number of bits effective number of bits (enob) indicates the global accuracy of an adc at a specific input frequency and sampling rate. an ideal adc s error consists of quanti- zation noise only. with an input range equal to the adc s full-scale range, calculate the enob as follows: total harmonic distortion total harmonic distortion (thd) is the rms sum ratio of the input signal s first five harmonics to the fundamental itself, expressed as: where v 1 is the fundamental amplitude, and v 2 through v 5 are the amplitudes of the 2nd- through 5th-order harmonics. spurious-free dynamic range spurious-free dynamic range (sfdr) is the ratio of rms amplitude of the fundamental (maximum signal compo- nent) to the rms value of the next-largest distortion component. chip information transistor count: 18,269 process: bicmos thd = ? ? ? ? ? ? ? ? 20 2 log v+v+v+v v 2 2 3 2 4 2 5 1 e sinad - 1.76 nob = ? ? ? ? ? ? 602 . sinad db ( ) log = ? ? ? ? ? ? 20 signal noise rms rms max1069 58.6ksps, 14-bit, 2-wire serial adc in a 14-pin tssop ______________________________________________________________________________________ 19
max1069 58.6ksps, 14-bit, 2-wire serial adc in a 14-pin tssop maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2002 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) tssop4.40mm.eps

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